Field of the Technology
The present invention relates to high density memory devices based on programmable resistive memory materials, and methods for operating such devices.
Description of Related Art
In a phase change memory (PCM), each memory cell includes a phase change memory element. The phase change memory element is made of phase change materials that exhibit a large resistivity contrast between crystalline (lower resistivity) and amorphous (higher resistivity) phases. Phase change materials may include alloys of materials such as germanium (Ge), antimony (Sb), tellurium (Te), gallium (Ga), indium (In), silver (Ag), selenium (Se), thallium (Ti), bismuth (Bi), tin (Sn), copper (Cu), palladium (Pd), lead (Pb), sulfur (S), and gold (Au).
In operation of a phase change memory element, an electrical current pulse passed through the phase change memory cell can set or reset the resistivity phase of the phase change memory element. To reset the memory element into the amorphous phase, an electrical current pulse with a large amplitude for a short time period can be used to heat up an active region of the memory element to a melting temperature, and then cool quickly causing it to solidify in the amorphous phase. To set the memory element into the crystalline phase, an electrical current pulse with a medium amplitude, which causes it to heat up to a crystallization temperature, and a longer cooling time period can be used allowing the active region to solidify in a crystalline phase. To read the state of the memory element, a small voltage is applied to the selected cell and the resulting electrical current is sensed.
Resistance drift is a well-known phenomenon in PCM. The resistance of memory cells increases with time, and follows the power-law relationship:
      R    ⁡          (      t      )        =                    R        o            ⁡              (                  t                      t            o                          )              γ  where R0 is the initial resistance at an initial time t0, R(t) is the resistance at a time t>t0, and γ is a resistance drift coefficient.
To recover the resistance drift in PCM memory devices, one approach is to use a DRAM-like (dynamic random-access memory) refresh scheme to reprogram multiple states in MLC PCM memory cells. In DRAM memory cells, electrical charge stored in the storage capacitors gradually leaks out through the access transistor. Consequently, to maintain data integrity, data values stored in the DRAM memory cells must be periodically read out and restored to their respective full voltage levels before the stored electrical charges decay to indistinguishable levels. DRAM refresh requires different actions for different logical levels, and the number of actions required is equal to the number of logical levels.
However, using a DRAM-like refresh scheme to recover resistance drift in PCM memory devices can be time-consuming and endurance-wasting, especially for MLC PCM devices. For example, for a 256 Mb (mega-bit) PCM chip, the estimated refresh time for the entire chip can be calculated as:
      Refresh    ⁢                  ⁢    Time    =                              (                      Chip            ⁢                                                  ⁢            Density                    )                                      (                          #              ⁢                                                          ⁢              Bit              ⁢                                                          ⁢              per              ⁢                                                          ⁢              Cell                        )                    ⁢                      (                          #              ⁢                                                          ⁢              Concurrent              ⁢                                                          ⁢              Writes                        )                              ⁢              (                  #          ⁢                                          ⁢          of          ⁢                                          ⁢          Program          ⁢                                          ⁢          Iteration                )            ⁢              (                  Program          ⁢                                          ⁢          Latency                )              =                            (                                    256              ×                              10                6                                                    2              ×              16                                )                ⁢                  (          7.2          )                ⁢                  (                      200            ⁢                                                  ⁢            ns                    )                    =              11.5        ⁢                                  ⁢        sec            where the verification time for programming MLC cells is omitted. Consequently the refresh time (e.g. 11.5 seconds) alone occupies about 13.4% of the total refresh interval which is set to the time to failure (e.g. 86 seconds).
Furthermore, using the DRAM-like refresh, endurance is wasted from periodic refreshes. For SLC (single level cell) memory cells, the total amount of endurance wasted in 10 years can be estimated as:
            SLC      ⁢                          ⁢      Endurance      ⁢                          ⁢      Wasted        =                            (                      10            ⁢                                                  ⁢            years                    )                          (                      Refresh            ⁢                                                  ⁢            Interval                    )                    =                                    (                          10              *              365              *              24              *              60              *              60                        )                                (            86            )                          =                              3.67            ×                          10              6                        ⁢                                                  ⁢            cycles                    ≈                      3.7            ⁢            %                                ,      assuming    ⁢                  ⁢          10      8        ⁢                  ⁢    cycling    ⁢                  ⁢          endurance      .      
For MLC (multi-level cell) memory cells, the total amount of endurance wasted in 10 years can be estimated as:MLC Endurance Wasted=(SLC Endurance Wasted)(# of MLC Program Iteration)=3.7%×7.2=26.6%, assuming 108 endurance.
Another drawback for the DRAM-like refresh is that it cannot correct erroneous resistance levels of a memory cell. If a memory cell has drifted to an erroneous state, the DRAM-like refresh simply re-programs the memory cell to the erroneous state. Therefore, to be conservative, the refresh interval for the DRAM-like refresh needs to be shorter than the time to failure (e.g. 86 seconds), as described in connection with FIG. 1B, during which the first erroneous state can occur. Consequently, shorter refresh intervals will increase both the performance and endurance penalties.
It is desirable to provide MLC PCM devices that can recover resistance drift without the performance and endurance penalties caused by a DRAM-like refresh.